1. Technical Field
The present invention relates to a MOSFET transistor comprising a gate made of silicon-germanium alloy and formed on a single-crystal silicon substrate by means of a thin insulating layer and drain and source regions implanted in the substrate on each side of the gate.
2. Description of the Related Art
One of the major trends in microelectronics today is to reduce the length of the gates of MOSFET transistors below 0.25 micrometer without degrading the electrical characteristics of these transistors. Beside the various technological problems to be solved to achieve this object, the so-called xe2x80x9cShort Channel Effectxe2x80x9d or SCE effect has to be faced, due to space charge regions appearing in the PN junctions, which are present at the channel/drain and channel/source interfaces of the MOS transistors. These regions, emptied of free carriers, reduce the useful length of the channel and the number of carriers available for the inversion region under the gate. The shortening of the channel not being controlled by the gate creates consequences including a substantial decrease of the threshold voltage Vth and an increase of the OFF current, i.e. the leakage current of the transistors in the OFF state.
It is known in the prior art that a gate made of germanium or of a silicon-germanium alloy increases the threshold voltage Vth of MOS transistors, in particular PMOS transistors. For example, the Patent application FR-97-08457 in the name of the same applicant provides, to that effect, a method of forming a gate made of an alloy Si1xe2x88x92xGex where xe2x80x9cxxe2x80x9d is above 50%.
In relation with FIG. 1, it is recalled that the threshold voltage of a MOS transistor indeed depends on the work function "PHgr" of the gate material, whose expression is:
"PHgr"=EG+"khgr"
With:
EG=Evxe2x88x92Ec
And:
"khgr"=E0xe2x88x92Ev
EG being the gap of the gate material, "khgr" the electron affinity of the gate material, E0 the energy level of the vacuum (free electron at rest), Ev the low limit and Ec the high limit of the gap.
The gap EG(Ge) of germanium, equal to 0.66 eV, being smaller than the gap EG(Si) of silicon, equal to 1.12 eV, the work function "PHgr"(Ge) of germanium is smaller than the work function "PHgr"(Si) of silicon. As the gate voltage is negative in a PMOS transistor, with regard to the substrate, the threshold voltage Vth of a transistor with a germanium gate is thus higher, in absolute value, than the threshold voltage Vth of a transistor with a silicon gate.
However, the providing of a gate made of germanium or germanium-silicon alloy brings only a relative advantage and does not allow the suppression of the short channel effect. To aid in better understanding, the graphs C1, C2, represented in FIG. 2, illustrate the variations of the threshold voltage Vth versus the length of the gate Lg, respectively, for a silicon gate and a germanium gate. The graph C2 of the transistors with a germanium gate, although being offset upwardly in absolute value compared to the graph C1 of the transistors with a silicon gate, presents the same decrease as the graph C1 when the length of the gate becomes less than 0.3 micrometer.
Within an integrated circuit, this rapid decrease of the graphs C1 and C2 below 0.3 micrometer involves a significant dispersion of the threshold voltages of transistors having different gate lengths. It also involves a dispersion of the threshold voltages of transistors having, theoretically, the same gate length, because of fabrication tolerances of the gates, typically in the order of 0.02 xcexcm. Lastly, transistors with a short channel and a small threshold voltage present a current consumption which is not negligible in the OFF state, as already mentioned.
Thus, a general object of the present invention is to provide a means allowing the compensation of the short channel effect in MOS transistors with a small gate length.
A more specific object of the present invention is to provide a means allowing gradual compensation for the short channel effect, in a way inversely proportional to the length of the gate Lg of MOS transistors, so as to straighten the graph Vth=f(Lg) up to gate lengths on the order of 0.1 xcexcm, or even less.
To that effect, the present invention provides a MOSFET transistor comprising a gate made of a silicon-germanium alloy, formed on a single crystal silicon substrate by means of a thin insulating layer, and drain and source regions implanted in the substrate on each side of the gate, wherein the gate comprises side regions presenting an increasing germanium percentage toward the edges of the gate facing the drain and source regions.
According to one embodiment, the gate comprises a silicon central region comprising no germanium or a constant percentage of germanium.
According to one embodiment, the side regions comprise a maximal germanium percentage ranging from 10 to 100% on the sides of the gate.
According to one embodiment, the transistor is of the PMOS type and comprises a P-type gate on a N-type substrate.
The present invention also relates to an integrated circuit comprising a plurality of transistors, according to the invention, and having gates of various lengths, wherein the side regions presenting an increasing germanium percentage are substantially of the same length, independent of the lengths of the gates, so that the gates with a smaller length comprise an average germanium percentage greater than the gates with a larger length.
The present invention also relates to a method of manufacturing a MOS transistor gate comprising an initial step of forming an initial gate made of silicon or silicon-germanium alloy with a small germanium percentage, the steps of depositing a germanium external layer at least on the sides of the gate, applying a thermal annealing cycle to the gate in order to diffuse germanium from the germanium external layer into the gate material, and removing the germanium external layer.
According to one embodiment, the step of depositing the germanium external layer is preceded by a step of depositing, at least on the sides of the gate, a thin layer of a protection material at least resistant to a solvent or an etching agent of the germanium external layer.
According to one embodiment, the protection material is silicon oxide.
According to one embodiment, the germanium external layer is removed according to one of the following processes: cleaning with water, cleaning with hydrogen peroxide, cleaning with sulphuric acid, removal by oxygen plasma, or a combination of these processes.
According to one embodiment, the initial gate is formed by etching a layer of gate material by means of a hard mask made of silicon oxide. The hard mask is left over the top of the gate during the germanium diffusion step, and the hard mask is removed from the gate after the germanium diffusion.
According to one embodiment, a further step of doping the gate by means of P-type dopant atoms is provided.